Programmable integrated-circuits are generally known and used to shorten design time, shorten processing time, or add flexibility to the art of circuit design.
The Massachusetts Institute of Technology (MIT) Lincoln Laboratory developed a laser-programmable logic module. This module is disclosed in U.S. Pat. No. 4,937,475, entitled "LASER PROGRAMMABLE INTEGRATED CIRCUIT." U.S. Pat. No. 4,937,475 is, hereby, incorporated by reference into the specification of the present invention.
It is desirable to have a programmable integrated-circuit that can be programmed with both open-circuits and short-circuits, contains sequential logic as well as combinatorial logic, is optimized for performance as well as area efficiency, can be synthesized easily, can be tested fully, and can be used in bus-intensive circuits. The combinatorial-logic circuit of U.S. Pat. No. 4,937,475 does not include sequential logic. Even though U.S. Pat. No. 4,937,475 can be used to build sequential circuits, the resulting circuit would not perform as well as a circuit that includes sequential logic in the basic logic cell. Also, the circuit of U.S. Pat. No. 4,937,475 cannot be accepted by a synthesis tool easily.
A synthesis tool, such as the one marketed by Synopsys, Inc. is used to optimize the intended circuit. That is, a designer would provide a hardware description of the intended circuit to the synthesis tool, and the synthesis tool would perform a Karnaugh-map-type reduction of the description. The hardware description of the circuit of U.S. Pat. No. 4,937,475 is quite complex and, therefore, not easily synthesized.
U.S. Pat. No. 4,240,094, entitled "LASER-CONFIGURED LOGIC ARRAY," discloses a laser-programmable combinatorial-logic circuit and a method of producing the same. The device of U.S. Pat. No. 4,240,094 suffers from the same disadvantages that U.S. Pat. No. 4,937,475 suffers from (i.e., no sequential-logic circuitry and not easily synthesized).
U.S. Pat. No. 4,758,746, entitled "PROGRAMMABLE LOGIC ARRAY WITH ADDED ARRAY OF GATES AND ADDED OUTPUT ROUTING FLEXIBILITY," discloses a laser-programmable (open-circuits only) sequential-logic circuit, but it is not optimized for performance or area. The circuit disclosed in U.S. Pat. No. 4,758,746 does not contain any buffering for the clock signal to the sequential-logic circuit (i.e., a flip-flop). Therefore, the number of loads seen by the clock signal is directly proportional to the number of logic cells used. Since performance is inversely proportional to the number of loads on the clock signal, the performance of the circuit of U.S. Pat. No. 4,758,746 is not optimal. The circuit of U.S. Pat. No. 4,758,746 appears to have been designed to handle many inputs. For most applications, a large number of inputs is not needed. The unused inputs, and the associated circuitry, represent wasted space. Designs that must be optimized for area cannot afford the luxury of having unnecessary circuitry.
U.S. Pat. No. 5,357,153, entitled "MACROCELL WITH PRODUCT-TERM CASCADE AND IMPROVED FLIP FLOP UTILIZATION," discloses a logic-programmable sequential-logic circuit as opposed to a laser-programmable circuit as the present invention does. The circuit of U.S. Pat. No. 5,357,153 does not have the flexibility, or the area efficiency, of the present invention.
U.S. Pat. No. 4,912,345, entitled "PROGRAMMABLE SUMMING FUNCTIONS FOR PROGRAMMABLE LOGIC DEVICES," discloses a sequential logic circuit that is programmable in the combinatorial-logic portion only. Such a circuit is less flexible than a circuit that is programmable in both the combinatorial-logic portion and the sequential-logic portion as the present invention is. Also, the circuit of U.S. Pat. No. 4,912,345 does not include a buffered clock signal, which entails less-than-optimal performance, and is not optimized for area.